MicroBoard+PmodNAV模块1

哈哈欢 · 发表于 2017-2-7 09:01:41

前言
建立好Microblaze的基础上，要使用LSM9DS1这个芯片。我购买了PmodNAV这个模块。digilent提供的ip没有doc，而且这个模块的
driver 就没有编写完成，只提供了PmodNAV.h PmodNAV.c两个写好的文件头。未来不知道会不会添加。没办法我要用，我就自己设计不用他的driver咯。自己弄一个玩咯。那我就先看看他们的设计吧。

主体
我使用了Digilent的PmodNAV模块，在使用digilent提供的IP中PmodNAV ，遇到了很多问题，现在分享一下，这个Library中提供的ip是基于vivado的。我先理解这些ip的设计思想，然后自己在edk中自己重新设计ip 介绍一下情况吧
这个ip中实例化了AXI GPIO , AXI QUADSPI 和digilent的pmod bridge。现在搞通这几个的关系。
开始
axi -gpio
首先看一下axi gpio的接口这个可以在PG144-AXI-GPIO这个文档找到。

这里很明显我们看到这里的I.O.T端口。这些端口在wrapper 之后会综合成

这里使用的是原语IOBUF，能看见。说下端口
I-> input
T->triple-state
O->output
IO->bidirectional
这简单英语不解释。
其中IO 这个端口会被引出。
现在就复制黏贴下这个原语的作用吧
IOBUF #( .DRIVE(12), // Specify the output drive strength .IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE" .IOSTANDARD("DEFAULT"), // Specify the I/O standard .SLEW("SLOW") // Specify the output slew rate) IOBUF_inst ( .O(O), // Buffer output .IO(IO), // Buffer inout port (connect directly to top-level port) .I(I), // Buffer input .T(T) // 3-state enable input, high=input, low=output); // End of IOBUF_inst instantiation这些代码相信都能看的明白。不解释来继续看gpio

GPIO的双通道的
pmod-bridge
现在看看bridge怎么实现
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.//--------------------------------------------------------------------------------//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015//Date : Fri Feb 05 15:23:13 2016//Host : WK116 running 64-bit major release (build 9200)//Command : generate_target pmod_concat.bd//Design : pmod_concat//Purpose : IP block netlist//--------------------------------------------------------------------------------`timescale 1 ps / 1 psmodule pmod_concat ( in_top_bus_I, in_top_bus_O, in_top_bus_T, in_top_uart_gpio_bus_I, in_top_uart_gpio_bus_O, in_top_uart_gpio_bus_T, in_top_i2c_gpio_bus_I, in_top_i2c_gpio_bus_O, in_top_i2c_gpio_bus_T, in_bottom_bus_I, in_bottom_bus_O, in_bottom_bus_T, in_bottom_uart_gpio_bus_I, in_bottom_uart_gpio_bus_O, in_bottom_uart_gpio_bus_T, in_bottom_i2c_gpio_bus_I, in_bottom_i2c_gpio_bus_O, in_bottom_i2c_gpio_bus_T, in0_I, in1_I, in2_I, in3_I, in4_I, in5_I, in6_I, in7_I, in0_O, in1_O, in2_O, in3_O, in4_O, in5_O, in6_O, in7_O, in0_T, in1_T, in2_T, in3_T, in4_T, in5_T, in6_T, in7_T, out0_I, out1_I, out2_I, out3_I, out4_I, out5_I, out6_I, out7_I, out0_O, out1_O, out2_O, out3_O, out4_O, out5_O, out6_O, out7_O, out0_T, out1_T, out2_T, out3_T, out4_T, out5_T, out6_T, out7_T); parameter Top_Row_Interface = "None"; parameter Bottom_Row_Interface = "None"; output [3:0] in_top_bus_I; input [3:0] in_top_bus_O; input [3:0] in_top_bus_T; output [1:0] in_top_uart_gpio_bus_I; input [1:0] in_top_uart_gpio_bus_O; input [1:0] in_top_uart_gpio_bus_T; output [1:0] in_top_i2c_gpio_bus_I; input [1:0] in_top_i2c_gpio_bus_O; input [1:0] in_top_i2c_gpio_bus_T; output [3:0] in_bottom_bus_I; input [3:0] in_bottom_bus_O; input [3:0] in_bottom_bus_T; output [1:0] in_bottom_uart_gpio_bus_I; input [1:0] in_bottom_uart_gpio_bus_O; input [1:0] in_bottom_uart_gpio_bus_T; output [1:0] in_bottom_i2c_gpio_bus_I; input [1:0] in_bottom_i2c_gpio_bus_O; input [1:0] in_bottom_i2c_gpio_bus_T; output in0_I; output in1_I; output in2_I; output in3_I; output in4_I; output in5_I; output in6_I; output in7_I; input in0_O; input in1_O; input in2_O; input in3_O; input in4_O; input in5_O; input in6_O; input in7_O; input in0_T; input in1_T; input in2_T; input in3_T; input in4_T; input in5_T; input in6_T; input in7_T; input out0_I; input out1_I; input out2_I; input out3_I; input out4_I; input out5_I; input out6_I; input out7_I; output out0_O; output out1_O; output out2_O; output out3_O; output out4_O; output out5_O; output out6_O; output out7_O; output out0_T; output out1_T; output out2_T; output out3_T; output out4_T; output out5_T; output out6_T; output out7_T;generate case (Top_Row_Interface) "GPIO": begin assign in_top_bus_I={out3_I,out2_I,out1_I,out0_I}; assign {out3_O,out2_O,out1_O,out0_O}=in_top_bus_O; assign {out3_T,out2_T,out1_T,out0_T}=in_top_bus_T; end "UART": begin assign in_top_uart_gpio_bus_I={out3_I,out0_I}; assign {out3_O,out0_O}=in_top_uart_gpio_bus_O; assign {out3_T,out0_T}=in_top_uart_gpio_bus_T; //assign in1_I=out1_I; assign in2_I=out2_I; assign out1_O = in1_O; //assign out2_O = in2_O; assign out1_T = 0; assign out2_T = 1; end "I2C": begin assign in_top_i2c_gpio_bus_I={out1_I,out0_I};//Input is I2C bus, output is to Pmod Pins assign {out1_O,out0_O}=in_top_i2c_gpio_bus_O; assign {out1_T,out0_T}=in_top_i2c_gpio_bus_T; assign out2_O = in2_O; assign out3_O = in3_O; assign out2_T = in2_T; assign out3_T = in3_T; assign in2_I = out2_I; assign in3_I = out3_I; end default: begin assign out0_O = in0_O; assign out1_O = in1_O; assign out2_O = in2_O; assign out3_O = in3_O; assign out0_T = in0_T; assign out1_T = in1_T; assign out2_T = in2_T; assign out3_T = in3_T; assign in0_I = out0_I; assign in1_I = out1_I; assign in2_I = out2_I; assign in3_I = out3_I; end endcase endgenerate generate case (Bottom_Row_Interface) "GPIO":begin assign in_bottom_bus_I={out7_I,out6_I,out5_I,out4_I}; assign {out7_O,out6_O,out5_O,out4_O}=in_bottom_bus_O; assign {out7_T,out6_T,out5_T,out4_T}=in_bottom_bus_T; end "UART": begin assign in_bottom_uart_gpio_bus_I={out7_I,out4_I}; assign {out7_O,out4_O}=in_bottom_uart_gpio_bus_O; assign {out7_T,out4_T}=in_bottom_uart_gpio_bus_T; assign out5_O = in5_O; assign out6_O = in6_O; assign out5_T = in5_T; assign out6_T = in6_T; assign in5_I = out5_I; assign in6_I = out6_I; end "I2C": begin assign in_bottom_i2c_gpio_bus_I={out5_I,out4_I}; assign {out5_O,out4_O}=in_bottom_i2c_gpio_bus_O; assign {out5_T,out4_T}=in_bottom_i2c_gpio_bus_T; assign out6_O = in6_O; assign out7_O = in6_O; assign out6_T = in6_T; assign out7_T = in7_T; assign in6_I = out6_I; assign in7_I = out7_I; end default: begin assign out4_O = in4_O; assign out5_O = in5_O; assign out6_O = in6_O; assign out7_O = in7_O; assign out4_T = in4_T; assign out5_T = in5_T; assign out6_T = in6_T; assign out7_T = in7_T; assign in4_I = out4_I; assign in5_I = out5_I; assign in6_I = out6_I; assign in7_I = out7_I; end endcase endgenerateendmodule 这个代码自己可以package一个IP看看。作用就是PMOD的接口那个在上那个在下。
现在看PMODNAV的管脚图

看到这里 5-6-11-12这里是vcc gnd
继续看

这个看不清可以在这下点击下载
来继续

这个图就是spi输出到pmod bridge的123端口对应的spi协议的3-wire 片选对应的是由GPIO来完成。
对应的123 对应pmod的234 端口，和上边的原理图不冲突
来继续看gpio

这里 GPIO的channel1通道输出
来继续看这个

然后看这个代码这个代码在上边可找到
PmodNAV_pmod_bridge_0_0 pmod_bridge_0 (.in0_I(axi_gpio_0_GPIO_TRI_I[3]), .in0_O(axi_gpio_0_GPIO_TRI_O[3]), .in0_T(axi_gpio_0_GPIO_TRI_T[3]), .in1_I(axi_quad_spi_0_SPI_0_IO0_I), .in1_O(axi_quad_spi_0_SPI_0_IO0_O), .in1_T(axi_quad_spi_0_SPI_0_IO0_T), .in2_I(axi_quad_spi_0_SPI_0_IO1_I), .in2_O(axi_quad_spi_0_SPI_0_IO1_O), .in2_T(axi_quad_spi_0_SPI_0_IO1_T), .in3_I(axi_quad_spi_0_SPI_0_SCK_I), .in3_O(axi_quad_spi_0_SPI_0_SCK_O), .in3_T(axi_quad_spi_0_SPI_0_SCK_T), .in_bottom_bus_I(axi_gpio_0_GPIO_TRI_I[2:0]&axi_gpio_0_GPIO_TRI_I[4]), .in_bottom_bus_O(axi_gpio_0_GPIO_TRI_O[2:0]&axi_gpio_0_GPIO_TRI_O[4]), .in_bottom_bus_T(axi_gpio_0_GPIO_TRI_T[2:0]&axi_gpio_0_GPIO_TRI_T[4]), .out0_I(pmod_bridge_0_Pmod_out_PIN1_I), .out0_O(pmod_bridge_0_Pmod_out_PIN1_O), .out0_T(pmod_bridge_0_Pmod_out_PIN1_T), .out1_I(pmod_bridge_0_Pmod_out_PIN2_I), .out1_O(pmod_bridge_0_Pmod_out_PIN2_O), .out1_T(pmod_bridge_0_Pmod_out_PIN2_T), .out2_I(pmod_bridge_0_Pmod_out_PIN3_I), 很明显。这里axi_gpio_0_GPIO_TRI_T[4]这个信号被接地。小节结束
整个的设计很多的坑让跳，不提供这些ip的说明。他们内部自己有。
其他完成的ip的driver 设计，想要实现类似于mbed arduino 还有他们的chipkit32那种库。但是完全还是用c写了 *.c * .h 整个代码还是呵呵。
还是不要用他们的driver吧。
下节再说吧。

MicroBoard+PmodNAV模块1

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